安谋科技arm CHINA 2025暑期实习生招聘 | 成就核芯 由你领航

先人一步的转正赛道

  参加2025暑期实习，表现优异者可直通校招Offer！

  研发项目实战=真Offer筹码！

中国智能计算生态领航者

安谋科技（中国）有限公司（“安谋科技”）是国内领先的芯片IP设计与服务提供商。作为一家独立运营的合资企业，公司立足本土创新，坚持以自研业务技术创新与Arm技术授权相配合，为中国集成电路产业提供丰富的产品组合和解决方案，赋能中国智能计算“芯”生态。

过去二十余年，安谋科技及前身Arm公司中国子公司积极开拓，持续赋能国内最具创新能力的移动、终端、智能物联网、汽车、数据中心等芯片设计领域。自2018年至今，安谋科技在国内的授权客户已超过430家，累计芯片出货量突破370亿片，拉动了下游年产值过万亿人民币规模的科技产业生态。

面向未来，安谋科技将秉承创新、奋斗、共赢的理念，大力投入本土研发，夯实数字经济时代技术底座，推动中国智能计算产业高质量发展。

招聘对象

毕业时间在2025年9月-2026年12月期间的在校大学生

*中国大陆（内地）以毕业证为准，中国港澳台及海外地区以学位证为准。

招聘流程

网申（5月）-面试（5月-6月）-Offer（6月）-入职 （6月-7月）

招聘岗位

自研IP团队，开放设计、验证、软件等实习岗位，实习岗位陆续上线中，覆盖上海、北京、深圳、成都四个城市，具体岗位介绍可在职位详情页查看。

简历投递方式

1.    微信关注“安谋科技招聘”官方微信号，点击“RecruitU”，进入校园招聘

2.    联系安谋科技的学长学姐进行内部推荐

3.    登录www.armchina.com，点击“招贤纳士”，进入校园招聘

更多问题，欢迎邮件至：recruitment@armchina.com

2025 Summer Intern-Algorithm Engineer (VPU)

职位描述

Responsibilities:

Video codec algorithm research and optimization;

C-Model design and implementation.

Cooperate with hardware engineers to optimize the performance of hardware modules and area;

Help hardware and system/FPGA engineers for system/FPGA verification;

Customer support in feature development and subjective optimization;

Requirements :

MS/PHD/in EE /CS or related IT technology fields;

Strong knowledge in video coding standards (H.264, HEVC, AV1, and VVC etc.) and video/image processing algorithms.

Experience in video codec algorithm research or video multimedia.

Experience in open source codecs (x264, x265, VVenC).

Familiar with hardware design and optimization;

Familiar with Neural Network-based image/video coding and processing；

Good Mandarin and English communication skills;

Good team work and effective working under high pressure.

2025 Summer Intern-Design/ Verification Engineer (VPU)

职位描述

Job Responsibility

As an IC/IP technologist, you will contribute to the RTL design of high performance, energy efficient accelerators and/or compute units for high performance compute IC/IP. Your responsibilities will be related, but not limited to

• Micro-architecture design.

• RTL logic design, debug and Verification (e.g. IP/methodologies/framework, bus functional models, regression tests).

Requirements:

• Master (MS) or Doctorial (Ph.D.) Degree in Electrical Engineering or Computer Science/Engineering.

• Familiarity or experience in RTL design with Verilog and/or VHDL is required.

• Familiar with C/C++ language.

• Experience or knowledge of FPGA design and debug.

• Fast learning skills.

Experience in following will be a plus:

• Video codec Hardware/Algorithm/model design.

• RTL design for multi-threaded, low-power microprocessors.

• A good understanding of SoC designs and system architecture.

2025 Summer Intern-Software Engineer (NPU)

Job Description:

This job will mainly focus on the following areas, but not limited to:

• Participate in AI toolchain development

• Participate in NPU runtime and driver development

• Participate in NPU building-tool development

• Participate in NPU operator library verification

Requirements:

• Major in EE, Computer science or related background

• The programming skills in C/C++/Python

• Familiar with the development tools such as Linux, Git, Makefile and sh

• Fast learning skills.

2025 Summer Intern-Design/ Verification Engineer (NPU)

职位描述

Job Description:

As a Graduate Hardware IP Engineer, you will contribute to RTL implementation / verification for Artificial Intelligence (AI) related IP and work on cutting-edge AI technique from ideas to implementation.

Your responsibilities will be related, but not limited to:

Learning AI related knowledge and apply to daily work

Working closely with software team for hardware-software co-design

NPU architecture modelling, micro-architecture design, RTL coding and quality check

Applying Verification skill and methodology to daily work, responsible for building a verification environment, debugging and verification quality check

Working under pressure to deliver IP to customer.

Skills and Experience:

Degree from EE. CS and good plus with qualifications from circuit design / computer science

Good understanding of modern computer architecture such as CPU / GPU / DSP / AI-accelerator architecture will be preferred

Good understanding of AI operators such as convolution, pooling etc., will be preferred

Good knowledge of Verilog / System Verilog / UVM

Proficient in using general-purpose programming languages: C/C++/Python

Proficiency in English writing

With excellent communication skill, teamwork and attention to details.